Design and Analysis of Low Power Charge Pump Circuit for Phase-locked Loop

CMOS is used to construct the integrated circuits with low level of static leakage. With this low level leakage we are designing all the transistor circuits in CMOS logic. To control this static leakage in the circuits the supply voltage is a major concern. Here the step-up converters with charge pump and the level for maintaining its threshold voltage (VT) is to be analyzed and proposed. Here we are going to propose the novel approach as body bias effect and sub-threshold logic. This will be applied for the step-up converters for energy harvesting applications. The backward control is to be processed for control the internal voltage when the charge transfer switch could be in activation. This will be used to boost the voltages from the circuit for step-up converters. When the supply voltage is to be raise from the fixed voltage level it will be turn OFF the transistor. The maximum level of the converters circuits contain the branch A and branch B which could be contains all p-MOS and n-MOS combinations. The oscillator circuit also to e designed and applied to the proposed six stage charge pump circuit to reduce the power consumption. To reduce the standby mode leakage we are designing the circuit by using power gating logic. These circuits are to be designed and verified by using the TANNER TSPICE TOOLS.